硬件原理圖如下：

CH9434的INT接SSD202D的TTL26，CS，CLK，MOSI，MISO，分別接SSD202D的GPIO8，GPIO9，GPIO10，GPIO11?。

參考SPI使用參考 - SigmaStarDocs (comake.online)，修改DTS，

修改arch\arm\boot\dts\infinity2m-ssc011a-s01a-padmux.dtsi

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把相關(guān)管腳復(fù)用成SPI，編譯kernel燒進(jìn)板子后，會(huì)有/dev/spidev0.0節(jié)點(diǎn)。

參考恒沁官網(wǎng)驅(qū)動(dòng)，修改ch9434驅(qū)動(dòng)，

1：屏蔽DTS，增加spi_info

2：增加spi_register_board_info

把驅(qū)動(dòng)編譯進(jìn)內(nèi)核后，跑起來后ch943x_scr_test一直不過。

[? ? 1.837296] [ss_gpi_intc_domain_alloc] hw:30 -> v:62

[? ? 1.839409] gpio_to_irq:62, spi->irq:60

[? ? 1.843310] change to SPI MODE 3!

[? ? 1.846561] [Padmux]reset Pad_45(reg 0x101e0d; mask0xf00) to GPIO(org: TTL_MODE_1)

[? ? 1.854279] ch943x_port_write - reg:0x81, val:0x 0

[? ? 1.858940] ch943x_port_write - reg:0x84, val:0x 0

[? ? 1.863760] ch943x_port_read - reg:0x 6, val:0xc7

[? ? 1.868389] ******Uart 0 SPR Test Start******

[? ? 1.872791] ch943x_port_write - reg:0x87, val:0x55

[? ? 1.877567] ch943x_port_read - reg:0x 7, val:0xc7

[? ? 1.882253] UART 0 SPR Test Failed.

[? ? 1.885725] ch943x_spi spi0.1: ch943x_probe error

[? ? 1.890431] ch943x_spi: probe of spi0.1 failed with error -1

spi_board_info中的irq以及其controller_data不知道如何取值。不清楚這樣修改是否正確？還請(qǐng)大神給與解答。

幫頂

1、驅(qū)動(dòng)能執(zhí)行到ch943x_spi_probe，說明驅(qū)動(dòng)已經(jīng)成功移植到系統(tǒng)，SPI總線-設(shè)備-驅(qū)動(dòng)已正常匹配；

2、ch943x_scr_test不過表示外圍硬件上存在問題，SPI主機(jī)和芯片通信失敗，建議用邏輯分析儀抓SPI硬件時(shí)序查看，可將原理圖和時(shí)序發(fā)至郵箱yz@wch.cn

hi，

我也遇到通信問題，ch943x_scr_test不過 ，量了cpu端的spi通信（回環(huán)測(cè)試）是正常的，量了ch9434的vdd vcc vcore 晶振都是正常的，就是目前量cpu到ch9434的波形時(shí)，clk有變化，mosi和clk一起變化，但是cs的電平一直為高，想請(qǐng)教下這個(gè)cs信號(hào)要怎么設(shè)置呢？

1：管腳復(fù)用需要修改DTS：

2：還需要修改公版DTS中的dma（默認(rèn)是1，需要屏蔽或者修改成0，原因未知）

3：修改驅(qū)動(dòng)中ch943x_spi_probe函數(shù)，把函數(shù)剛開始的dev_dbg換成printk，否則ch943x_scr_test也過不了。

修改上面幾處之后，可以正常加載ko。結(jié)果如下：

root@SmartGateway:/tmp# insmod ch9434.ko

[? ?16.582673] ch9434: SPI serial driver for ch9434.

[? ?16.584531] ch9434: V1.1 On 2023.04

[? ?16.588236] [ss_gpi_intc_domain_alloc] hw:30 -> v:65

[? ?16.593443] gpio_to_irq:65, spi->irq:64

[? ?16.596829] ch943x_spi spi0.1: change to SPI MODE 3!

[? ?16.602195] ch943x_spi spi0.1: ch943x_port_write - reg:0x81, val:0x 0

[? ?16.608234] ch943x_spi spi0.1: ch943x_port_write - reg:0x84, val:0x 0

[? ?16.615005] ch943x_spi spi0.1: ch943x_port_read - reg:0x 6, val:0x11

[? ?16.621830] ch943x_spi spi0.1: ******Uart 0 SPR Test Start******

[? ?16.627086] ch943x_spi spi0.1: ch943x_port_write - reg:0x87, val:0x55

[? ?16.633914] ch943x_spi spi0.1: ch943x_port_read - reg:0x 7, val:0x55

[? ?16.639849] ch943x_spi spi0.1: ch943x_port_write - reg:0x87, val:0xaa

[? ?16.646590] ch943x_spi spi0.1: ch943x_port_read - reg:0x 7, val:0xaa

[? ?16.652758] ch943x_spi spi0.1: ******Uart 0 SPR Test End******

[? ?16.658459] ch943x_spi spi0.1: ch943x_port_write - reg:0x91, val:0x 0

[? ?16.665145] ch943x_spi spi0.1: ch943x_port_write - reg:0x94, val:0x 0

[? ?16.671490] ch943x_spi spi0.1: ch943x_port_read - reg:0x16, val:0x 0

[? ?16.678463] ch943x_spi spi0.1: ******Uart 1 SPR Test Start******

[? ?16.683796] ch943x_spi spi0.1: ch943x_port_write - reg:0x97, val:0x55

[? ?16.690191] ch943x_spi spi0.1: ch943x_port_read - reg:0x17, val:0x55

[? ?16.696953] ch943x_spi spi0.1: ch943x_port_write - reg:0x97, val:0xaa

[? ?16.703100] ch943x_spi spi0.1: ch943x_port_read - reg:0x17, val:0xaa

[? ?16.709251] ch943x_spi spi0.1: ******Uart 1 SPR Test End******

[? ?16.715359] ch943x_spi spi0.1: ch943x_port_write - reg:0xa1, val:0x 0

[? ?16.721722] ch943x_spi spi0.1: ch943x_port_write - reg:0xa4, val:0x 0

[? ?16.727996] ch943x_spi spi0.1: ch943x_port_read - reg:0x26, val:0x11

[? ?16.735225] ch943x_spi spi0.1: ******Uart 2 SPR Test Start******

[? ?16.740407] ch943x_spi spi0.1: ch943x_port_write - reg:0xa7, val:0x55

[? ?16.747252] ch943x_spi spi0.1: ch943x_port_read - reg:0x27, val:0x55

[? ?16.753397] ch943x_spi spi0.1: ch943x_port_write - reg:0xa7, val:0xaa

[? ?16.759592] ch943x_spi spi0.1: ch943x_port_read - reg:0x27, val:0xaa

[? ?16.766171] ch943x_spi spi0.1: ******Uart 2 SPR Test End******

[? ?16.771926] ch943x_spi spi0.1: ch943x_port_write - reg:0xb1, val:0x 0

[? ?16.778368] ch943x_spi spi0.1: ch943x_port_write - reg:0xb4, val:0x 0

[? ?16.784687] ch943x_spi spi0.1: ch943x_port_read - reg:0x36, val:0x 0

[? ?16.791864] ch943x_spi spi0.1: ******Uart 3 SPR Test Start******

[? ?16.797068] ch943x_spi spi0.1: ch943x_port_write - reg:0xb7, val:0x55

[? ?16.803919] ch943x_spi spi0.1: ch943x_port_read - reg:0x37, val:0x55

[? ?16.809833] ch943x_spi spi0.1: ch943x_port_write - reg:0xb7, val:0xaa

[? ?16.816577] ch943x_spi spi0.1: ch943x_port_read - reg:0x37, val:0xaa

[? ?16.822732] ch943x_spi spi0.1: ******Uart 3 SPR Test End******

[? ?16.828449] ch943x_spi spi0.1: ch943x_probe - firmware version: V1.0

[? ?16.835037] ch943x_spi spi0.1: ch943x_port_write - reg:0xc8, val:0xcd

[? ?17.041482] ch943x_spi spi0.1: ch943x_probe - devm_request_threaded_irq =64 result:0

[? ?17.046405] ch943x_spi spi0.1: sysfs_create_group() succeeded!!

root@SmartGateway:/tmp#? [? 372.147407] random: crng init done

root@SmartGateway:/tmp# ls /dev/ttyWCH*

/dev/ttyWCH0? /dev/ttyWCH1? /dev/ttyWCH2? /dev/ttyWCH3

root@SmartGateway:/tmp#??

還有一個(gè)修改點(diǎn)：終端的觸發(fā)方式得有默認(rèn)的IRQF_TRIGGER_LOW改為IRQF_TRIGGER_RISING；

根據(jù)irq-gpi.c中代碼，只支持IRQ_TYPE_EDGE_FALLING和IRQ_TYPE_EDGE_RISING，實(shí)測(cè)只有IRQ_TYPE_EDGE_RISING才能正常。

您好，因芯片的硬件中斷信號(hào)是低電平有效，通常在驅(qū)動(dòng)程序的配置上，可配置成：IRQF_TRIGGER_LOW 或?IRQF_TRIGGER_FALLING。其他中斷配置方式即使中斷可用也存在丟中斷導(dǎo)致業(yè)務(wù)異常的可能。

此外，建議可以用其他通用GPIO口模擬中斷給INT引腳，實(shí)測(cè)下中斷的觸發(fā)是否和設(shè)置匹配。

ch9434.zip

附件是根據(jù)建議修改好的驅(qū)動(dòng)文件。串口收發(fā)自測(cè)正常。