假定，程序只有 一個(gè) INT0 外部中斷，下降沿中斷，優(yōu)先級高。（即不考慮程序的影響，單純硬件上考慮）
當(dāng)外部發(fā)生下降沿， 單片機(jī)保存 PC地址 然后跳轉(zhuǎn)到 0003
請問，從下降沿發(fā)生，到從0003地址開始執(zhí)行 代碼，這個(gè)過程，總共會經(jīng)歷多少個(gè)系統(tǒng)時(shí)鐘？
加強(qiáng)型51機(jī)器周期和時(shí)鐘周期幾乎一致，運(yùn)行跳轉(zhuǎn)中斷，大概會經(jīng)過兩次跳轉(zhuǎn)，可以轉(zhuǎn)成匯編看下具體的代碼查看用到的指令條數(shù)，具體的指令及其對應(yīng)的周期數(shù)可以參考這個(gè)文檔：
http://www.findthetime.net/downloads/CH554EVT_ZIP.html
EVT->PUB->CH55X匯編指令.PDF
你好，指令周期我會看，我本來就是用匯編寫的代碼，所以不用轉(zhuǎn)，你給我指令周期表，我不知道有什么用，從外部中斷0 觸發(fā)下降沿，到PC指針 指向0x0003這個(gè)過程，指令周期表上能查到？我所需要知道的，就是從外部給信號，到單片機(jī)PC指針跳轉(zhuǎn)到 0x0003這個(gè)地址為止，需要多少時(shí)間？？
Latency should be at most the execution time of LCALL + 7
worst is 12 clocks
best is 6 clocks
@usbman
The?Latency information is useful. Is there any source for that kind of info?
its hard to find realable sources for that these days. Maybe this helps:
Understanding Interrupt Latency in Modern 8051s — CAST Technical Article | ChipEstimate.com
some explanations:
before a interrupt is accepted the last cmd must terminate. On an old 12 clocker this can eat up to 48 cycles (MUL / DIV) ON E8051 its 6/7clocks?
executing the irq vector is like a LCALL 0x0003
at irq vector most of the time there ist LJMP ISR_Routine which adds another 6/7 cycles
if there is already another irq running with the same priority the runtime of that irq must be added too.
so in fact before the first cmt of the ISR_Routine is executed it takes 7 + 2 * 7 clocks at worse
or 1 + 2*6 at best. Also the priority reg must be reviewed when more than one IRQ source is enabled.
These calulations are just for a idle system using the exec times published from WCH.
Maybe one of the FAEs can put some extra light on that.
Thank you for your explanation.?
I tried to have the main code to flip an IO, and flip another IO at the beginning of Interrupt handler. The latency is about 14 clock. That is about 2 of the LJMP.
