Open On-Chip Debugger 0.11.0+dev-02415-gfad123a16-dirty (2023-09-22-10:36)

Licensed under GNU GPL v2

For bug reports, read

http://openocd.org/doc/doxygen/bugs.html

Info : only one transport option; autoselect 'sdi'

Warn : Transport "sdi" was already selected

Ready for Remote Connections

Started by GNU MCU Eclipse

Info : Listening on port 6666 for tcl connections

Info : Listening on port 4444 for telnet connections

Info : WCH-LinkE? mode:RV version 2.11?

Info : wlink_init ok

Info : clock speed 6000 kHz

Info : [wch_riscv.cpu.0] datacount=2 progbufsize=8

Info : [wch_riscv.cpu.0] Examined RISC-V core; found 1 harts

Info : [wch_riscv.cpu.0]? XLEN=32, misa=0x40901105

[wch_riscv.cpu.0] Target successfully examined.

Info : starting gdb server for wch_riscv.cpu.0 on 3333

Info : Listening on port 3333 for gdb connections

Info : accepting 'gdb' connection on tcp/3333

Info : device id = 0x14e2abcd

Info : flash size = 32kbytes

Warn : Prefer GDB command "target extended-remote :3333" instead of "target remote :3333"

Info : [wch_riscv.cpu.0] Found 0 triggers

Error: unable to step rtos hart

Error: failed read at 0x11, status=5978950

Error: Maybe the device has been removed

Assertion failed: target->arch_info, file ./src/target/riscv/riscv.h, line 279

為什么

Error: OpenOCD only supports Debug Module version 2 (0.13) and 3 (1.0), not 15 (dmstatus=0xffffffff). This error might be caused by a JTAG signal issue. Try reducing the JTAG clock speed.

Error: [wch_riscv.cpu.0] Hart is unavailable.

Error: [wch_riscv.cpu.0] Hart doesn't exist.

Info : [wch_riscv.cpu.0] Hart unexpectedly reset!

undefined debug reason 8 - target needs reset

Error: OpenOCD only supports Debug Module version 2 (0.13) and 3 (1.0), not 0 (dmstatus=0x0). This error might be caused by a JTAG signal issue. Try reducing the JTAG clock speed.

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